SAK-TC264D-40F200W BC Infineon
Available
SAK-TC264D-40F200W BC Infineon
The TC26x product family has the following features: • High Performance Microcontroller with two CPU cores • One 32-bit super-scalar TriCore CPUs (TC1.6P), having the following features: – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Multiply-accumulate unit able to sustain 2 MAC operations per cycle – up to 200 MHz operation at full temperature range – up to 120 Kbyte Data Scratch-Pad RAM (DSPR) – up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR) – 16 Kbyte Instruction Cache (ICACHE) – 8 Kbyte Data Cache (DCACHE) • Power Efficient scalar TriCore CPU (TC1.6E), having the following features: – Binary code compatibility with TC1.6P – up to 200 MHz operation at full temperature range – up to 72 Kbyte Data Scratch-Pad RAM (DSPR) – up to 16 Kbyte Instruction Scratch-Pad RAM (PSPR) – 8 Kbyte Instruction Cache (ICACHE) – 0.125Kbyte Data Read Buffer (DRB) • Lockstepped shadow core for TC1.6P • Multiple on-chip memories – All embedded NVM and SRAM are ECC protected – up to 2.5 Mbyte Program Flash Memory (PFLASH) – up to 96 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 0 Kbyte Memory (LMU) – BootROM (BROM) • 48-Channel DMA Controller with safe data transfer • Sophisticated interrupt system (ECC protected) • High performance on-chip bus structure – 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between busmasters, CPUs and memories – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (SFI Bridge) • Safety Management Unit (SMU) handling safety monitor alarms • Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU) • Hardware I/O Monitor (IOM) for checking of digital I/O • Versatile On-chip Peripheral Units – Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud – Four Queued SPI Interface Channels (QSPI) with master and slave capability upto 50 Mbit/s – High Speed Serial Link (HSSL) for serial inter-processor communication up to 320Mbit/s
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices – One MultiCAN+ Module with 5 CAN nodes and 256 free assignable messageobjects for high efficiency data handling via FIFO buffering and gateway data transfer – 6 Single Edge Nibble Transmission (SENT) channels for connection to sensors – One FlexRayTMmodule with 2 channels (E-Ray) supporting V2.1 – One Generic Timer Module (GTM) providing a powerful set of digital signal filteringand timer functionality to realize autonomous and complex Input/Output management – One Capture / Compare 6 module (Two kernels CCU60 and CCU61) – One General Purpose 12 Timer Unit (GPT120) – Three channel Peripheral Sensor Interface conforming to V1.3 (PSI5) – Peripheral Sensor Interface with Serial PHY (PSI5-S) – Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1 – IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH) • 8-bit Standby Controller (TC2x_SCR) – Two 8-bit timers – One 16-bit timer – Timer 2 Capture Compare Unit – Real Time Clock – Universal Asynchronous Receiver/Transmitter – High Speed Synchronous Serial Interface – Wake-up CAN Filter • Versatile Successive Approximation ADC (VADC) – Cluster of 4 independent ADC kernels – Input voltage range from 0 V to 5.5V (ADC supply) • Delta-Sigma ADC (DSADC) – Three/Four channels • Digital programmable I/O ports • On-chip debug support for OCDS Level 1 (CPUs , DMA, On Chip Buses) • Dedicated Emulation Device chip available (ED) – multi-core debugging, real time tracing, and calibration – Aurora Gigabit Trace Port (AGBT) on some variants (See below) – four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface • Power Management System and on-chip regulators • Clock Generation Unit with System PLL and Flexray PLL • Embedded Voltage Regulator
The TC26x product family has the following features: • High Performance Microcontroller with two CPU cores • One 32-bit super-scalar TriCore CPUs (TC1.6P), having the following features: – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Multiply-accumulate unit able to sustain 2 MAC operations per cycle – up to 200 MHz operation at full temperature range – up to 120 Kbyte Data Scratch-Pad RAM (DSPR) – up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR) – 16 Kbyte Instruction Cache (ICACHE) – 8 Kbyte Data Cache (DCACHE) • Power Efficient scalar TriCore CPU (TC1.6E), having the following features: – Binary code compatibility with TC1.6P – up to 200 MHz operation at full temperature range – up to 72 Kbyte Data Scratch-Pad RAM (DSPR) – up to 16 Kbyte Instruction Scratch-Pad RAM (PSPR) – 8 Kbyte Instruction Cache (ICACHE) – 0.125Kbyte Data Read Buffer (DRB) • Lockstepped shadow core for TC1.6P • Multiple on-chip memories – All embedded NVM and SRAM are ECC protected – up to 2.5 Mbyte Program Flash Memory (PFLASH) – up to 96 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 0 Kbyte Memory (LMU) – BootROM (BROM) • 48-Channel DMA Controller with safe data transfer • Sophisticated interrupt system (ECC protected) • High performance on-chip bus structure – 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between busmasters, CPUs and memories – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (SFI Bridge) • Safety Management Unit (SMU) handling safety monitor alarms • Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU) • Hardware I/O Monitor (IOM) for checking of digital I/O • Versatile On-chip Peripheral Units – Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud – Four Queued SPI Interface Channels (QSPI) with master and slave capability upto 50 Mbit/s – High Speed Serial Link (HSSL) for serial inter-processor communication up to 320Mbit/s
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices – One MultiCAN+ Module with 5 CAN nodes and 256 free assignable messageobjects for high efficiency data handling via FIFO buffering and gateway data transfer – 6 Single Edge Nibble Transmission (SENT) channels for connection to sensors – One FlexRayTMmodule with 2 channels (E-Ray) supporting V2.1 – One Generic Timer Module (GTM) providing a powerful set of digital signal filteringand timer functionality to realize autonomous and complex Input/Output management – One Capture / Compare 6 module (Two kernels CCU60 and CCU61) – One General Purpose 12 Timer Unit (GPT120) – Three channel Peripheral Sensor Interface conforming to V1.3 (PSI5) – Peripheral Sensor Interface with Serial PHY (PSI5-S) – Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1 – IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH) • 8-bit Standby Controller (TC2x_SCR) – Two 8-bit timers – One 16-bit timer – Timer 2 Capture Compare Unit – Real Time Clock – Universal Asynchronous Receiver/Transmitter – High Speed Synchronous Serial Interface – Wake-up CAN Filter • Versatile Successive Approximation ADC (VADC) – Cluster of 4 independent ADC kernels – Input voltage range from 0 V to 5.5V (ADC supply) • Delta-Sigma ADC (DSADC) – Three/Four channels • Digital programmable I/O ports • On-chip debug support for OCDS Level 1 (CPUs , DMA, On Chip Buses) • Dedicated Emulation Device chip available (ED) – multi-core debugging, real time tracing, and calibration – Aurora Gigabit Trace Port (AGBT) on some variants (See below) – four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface • Power Management System and on-chip regulators • Clock Generation Unit with System PLL and Flexray PLL • Embedded Voltage Regulator
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